An embodiment of the invention generally pertains to large scale integration memory integrated circuits (ICs) that may be used for data storage in a computer, and more particularly to the modeling and computer aided design and testing of such ICs.
Applicants wish to use semiconductor IC manufacturing techniques to drive the development of re-usable IC designs. Computer aided design (CAD) tools such as memory compilers have been developed that allow an IC designer to more efficiently design and verify the operation of a memory component, prior to starting the complex and costly volume manufacturing process for it. A memory component design or intellectual property (IP) component is generated using the compiler that meets a stated performance specification system. This memory IP component may be re-used, to become part of different manufactured IC packages. These include dedicated memory IC packages and a system on a chip (SoC) with embedded memory.
Memory is typically implemented as an array of storage cells, where each cell stores a discrete bit of information (e.g. a binary storage cell can store either a “0” or a “1”). Column and row decoding logic in the memory maps an externally provided address into a selection of one or more of the cells. Once selected, the cells can be either written into or read from, depending on the external command. To test memory, a test engine generates a predefined data pattern which is written to a given address range, and then some time later the given address range is read back. The test engine compares the results of the read with the predefined data pattern, to see if there is any difference that would indicate an error in the memory's operation.
An effective way to test a large scale memory IC is to fill the memory with a particular type of data background (DB). The following are some example DB patterns: solid (all memory cells are filled with “0”, or its inverse in which all memory cells are filled with “1”); checkerboard (alternating pattern of “0”s and “1”s in both the row and column directions, or its inverse); and row stripe (rows filled with “0”s alternate with rows filled with “1”s, or its inverse). The proper DB to use depends on the type of fault or defect to be detected.
As explained above, a DB pattern stored in an array of memory cells is generic in that the basic, internal appearance of the pattern would be the same for different types or different sizes of memories. However, the address sequences and data patterns needed on the outside of a memory, to obtain a particular DB pattern, may be different for other types or sizes of memories. That is because the physical or topological internal structure of memory in an IC chip differs from its logical structure that is seen by the user from outside the chip. This effect is referred to as scrambling. For example, logically adjacent addresses may not be physically adjacent (this is called address scrambling), and logically adjacent data bits may not be physically adjacent (this is called data scrambling).
Memory testing also calls for the test engine to determine the physical location of a fault, so that a repair can be affected. For instance, when a faulty cell has been located as being in a particular column, that column can be replaced by a redundant column in the memory (by rerouting address and data signals of the faulty column to the redundant one.) This is also referred to as memory diagnosis and repair. Memory diagnosis may also call for generating a bitmap view of the defective cells in the memory. To do so, the designer of a system IC typically manually extracts information about the physical topology of a memory design from its CAD layout file (that has been produced by a memory compiler), as needed to solve particular test problems. For example, to find the logical address and data sequences needed to write a given DB pattern (the “logical model”), the system IC designer reviews the CAD layout file to determine several physical aspects of the memory design that will impact the logical model. This involves reviewing the layout file to determine data scrambling and bit-line twisting, for example, and then using that information to determine the particular logical address and data sequences needed. The system IC designer then authors a piece of computer code into which these results are incorporated, where this piece of code implements the functionality of generating the DB pattern (the logical model) within the memory's test engine. The test engine so designed becomes a part of the memory (once manufactured) and is able to quickly generate the DB pattern for testing.